Design-Reuse

ARC introduces 16/32-bit instruction set architecture to reduce memory requirements by up to 30 per cent

ARC's configurable processor adds the ability to run both 16 and 32-bit instructions on a 32-bit architecture, allowing designers to reduce memory requirements by up to 30%, resulting in both lower ...
EDN

Understanding Assembly Language for IA-32 and Intel 64 Architectures – Part 1: Basic overview and instruction set extensions

First, architecture basics are detailed with information on the register sets, data types, and memory and instruction formats. Next, instruction set extensions are detailed, which include Intel® ...
Electronic Design

Second-Gen Instruction Set Reduces IP Cores’ Instruction Memory

Cortus released the APS23 and APS25 32-bit processor IP cores, based on v2 of the company’s instruction set. The new instruction set aims to reduce the size of a system’s instruction memory, usually ...
ZDNet

Clearing up the 32/64-bit memory limit confusion

Vista x64 can use more memory than the 32-bit version, which is limited to 4 gigabytes. The problem with this statement is that it gives the impression that the cut off point when it comes to memory ...
Design-Reuse

Lexra Announces the Fastest 32-BIT RISC Core to Execute MIPS® Instructions*

WALTHAM, MASS (July 19, 1999) – Lexra, a leading developer of processor cores for embedded applications, announced today the LX4280, the fastest 32-bit RISC core available to support the MIPS I® ...